This project was created using Wokwi and submitted to Tiny Tapeout for fabrication. The goal is to create a fully configurable, burst PRBS output. See Wiki for implementation details of PRBS and details on the operations of and polynomials for Linear-Feedback-Shift-Registers (LFSR).
The 8-bit PRBS generator has several 8-bit registers that are used to configure the output. Using the Tiny Tapeout board that is supplied with each project, the PRBS generator will take in a clock of any frequency output by the RP2040. The input clock is divided by the configured factor of 2, then this frequency is used to run the generator. The bit length and the polynomial of the output are configured in the registers. The output of the PRBS generator starts when the enable pin is set high.
There are 2 counters that control the output of the PRBS generator. The binary sequence will run for a configured number of times, with an output "clock" indicating this "rate". For Example, if the register is set to 20, the PRBS will be repeated 10 times, the output clock goes low, then another 10 times, and the output clock goes high. The idea behind this clock output is to signal to an external device for sending data. When the output clock goes low, the data needs to be set. When the output clock goes high, the data on the input pin is clocked in for the remainder of the output clock period.
The data bit is XOR'ed with the PRBS output to create a non-inverted or inverted sequence. Another register is configured to have the number of data bits that will be clocked into the PRBS generator. This number of data bits is the number of clock periods that are given from the output clock. Once the number of data bits has been completed, the PRBS generator automatically stops running. The generator remains off until the enable pin goes low, which resets the generator, and then high again to start another "data bits" cycles of the PRBS.
Registers are configured using SPI. For setting up each 8-bit register, the first byte sent is the command byte and must be hexadecimal 0x80 plus the address of the register to be configured. The second byte sent is the data that will be placed in the register and stored until changed or reset. The address field is the last 3-bits of the command byte and valid range is 1-5. Chip select high resets the command byte, and only 1 register may be written to per cycle of chip select.
A debug setup has been included for easy setup and testing. The debug mode sets the generator to divide the input clock by 16, the sequences per data bit to 7, the data bits count to 7, enables bits 0x0F (4 bits), and the polynomial to 0x0C (x^4 + x^3 + 1). To use the debug feature, start by placing all inputs low (including RST_N) to reset all registers and counters. Then:
The PRBS generator is now running, and the data line can be toggled to invert the output. Once the PRBS has repeated 49 times, the generator will stop. To start the sequence again, toggle the enable line.
Note: While the DEBUG line is high, all registers will be non-configureable. To use the SPI and configure the PRBS generator, set the DEBUG line low.
5 registers control the PRBS generator
Addressing and commands happen in a single CS session.
Reset_N clears all registers
(All DIO are set to output and used for debug purposes.)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| C0 | X | X | X | X | A2 | A1 | A0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| X | X | X | X | X | D2 | D1 | D0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| C7 | C6 | C5 | C4 | C3 | C2 | C1 | C0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| E8 | E7 | E6 | E5 | E4 | E3 | E2 | E1 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| E8 | E7 | E6 | E5 | E4 | E3 | E2 | E1 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| x^8 | x^7 | x^6 | x^5 | x^4 | x^3 | x^2 | x^1 |
* Do not address the command byte register, address 0. If the command byte is written to as
data, then the data could trigger the command byte to transfer to another register,
whose address is based on the contents of bits 0-2 when bit 7 is triggered.
** Clock divider bits 3-7 are unused and have no effect.
*** How the counters operate, a count of "0" is considered to be 65,536. Additionally, a count
of "1" does not work as expected, and is equivalent to a count of "0".
**** Bits must be enabled sequentially, starting with bit 0. Any bit enable value that is not
sequential is an undefined state. I do not believe it will break anything, but I have not
looked into what this will do to the output.
***** Enabling an XOR tap bypasses the bit enable register setting. For example, if bits 0-4 are
enabled but bit 6 has the XOR tap set, then the output polynomial will be x^6 + the rest
of the polynomial settings.
Connection to SPI port, clock input, and analyzer to observe.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | spi_cs | prbs_out_1 | debug_out_reg_sel_0 |
| 1 | spi_clk | prbs_out | debug_out_reg_sel_1 |
| 2 | spi_mosi | prbs_out_n | debug_out_reg_sel_2 |
| 3 | output_en | prbs_out_n_1 | debug_out_prbs_clk_bypass |
| 4 | data_in | data_clk | debug_out_data_count_clk |
| 5 | busy | debug_out_data_count_comb_out | |
| 6 | debug_out_system_clk | debug_out_seq_count_comb_out | |
| 7 | debug_setup | debug_out_prbs_clk |