This project implements 6 programmable digital LIF neurons. The neurons are arranged in 2 layers (3 in each). Spikes_in directly maps to the inputs of the first layer neurons. When an input spike is received, it is first multiplied by an 8 bit weight, programmable from the spi interface, 1 per input neuron. This 8 bit value is then added to the membrane potential of the respective neuron.
When the first layer neurons activate, its pulse is routed to each of the 3 neurons in the next layer. There are 9 programmable weights describing the connectivity between the first and second layers. Output spikes from the 2nd layer drive spikes_out.
After reset, program the neuron threshold, leak rate, and refractory period. Additionally program the first and 2nd layer weights (all programming is done over spi). Once programmed activate spikes_in to represent input data, track spikes_out synchronously (1 clock cycle pulses).
fpga
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ui_in[7] - unused | uo_out[7] - unused | GPIO pins are wired to outputs and driven high (unused by the design). |
| 1 | ui_in[6] - unused | uo_out[6] - unused | |
| 2 | ui_in[5] - spikes_in[2] | uo_out[5] - unused | |
| 3 | ui_in[4] - spikes_in[1] | uo_out[4] - unused | |
| 4 | ui_in[3] - spikes_in[0] | uo_out[3] - cipo | |
| 5 | ui_in[2] - copi | uo_out[2] - spikes_out[2] | |
| 6 | ui_in[1] - cs_n | uo_out[1] - spikes_out[1] | |
| 7 | ui_in[0] - sclk | uo_out[0] - spikes_out[0] |