Uses a set of registers to divide the clock.
Both 8 bit input are used for the divider
Can divide up to 65565, target uses 20 Mhz as example.
After reset, the clock should be divided by the input a 20MHz input clock. Experiment by changing the inputs
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | division input bit 0 | uo_out[0] clock output | division input bit 8 |
| 1 | division input bit 1 | Random Number Output | division input bit 9 |
| 2 | division input bit 2 | Random Number Output | division input bit 10 |
| 3 | division input bit 3 | Random Number Output | division input bit 11 |
| 4 | division input bit 4 | Random Number Output | division input bit 12 |
| 5 | division input bit 5 | Random Number Output | division input bit 13 |
| 6 | division input bit 6 | Random Number Output | division input bit 14 |
| 7 | division input bit 7 | Random Number Output | division input bit 15 |