334 Neural Network dinamic

334 : Neural Network dinamic

  • Author: Kevin Gajardo, David Tapia
  • Description: One line description
  • GitHub repository
  • Clock: 66000000 Hz

How it works

The project consists of a neural network of 4 (parameterizable and reusable) neurons, thanks to control signals.

From an 8-bit input, the inputs will be introduced into a reusable neural network of 4 neurons. Through a shift register, 4 different inputs are captured. Furthermore, thanks to a state machine, the parameters associated with each neuron are obtained: 4 weights and 1 bias, in total 20 parameters per network layer.

State changes are made using a binary signal, where the input data and neuron parameters are received and then the neurons are fed back their outputs to the next layer. To observe the network's output one need to bring the state machine to the first state using the pin "Finished", then, in the next 4 clock cycles the outputs of the neurons 3 to 0 will be shown on the output at the same time some new external inputs can be introduced to a new neural network without the need for a reset

State Description
State_IN The inputs of the neurons are found entering and the outputs are shown.
State_BUFF Neuron inputs are maintained while network parameters are entered
State_OUT Feedback of neurons with their previous result

Below is the structure for inputting the neurons entries:

ChipUSM1 (1)

Node A corresponds to the output of the state machine, and node B to the parameters for each neuron.

Regarding the parameters, they are fed in sequence, from neuron 3 to neuron 0. And the weights correspond to powers of 2, so, if w00=3, the input0 to the neuron0 will be multiplied by 2³.

ChipUSM2

How to test

The input signals must be coordinated to achieve correct testing, where the following order must be followed to enter the inputs and parameters considering multiple layers.

in_3 > in_2 > in_1 > in_0 > b3 > w33 > w32 > w31 > w30 > b2 > w23 > w22 > w21 > w20 > b1 > w13 > w12 > w11 > w10 > b0 > w03 > w02 > w01 > w00

Each entry must be maintained for 2 clk, to be captured on the rising edge and thus there is displacement with the shift registers.

External hardware

An FPGA is recomended in to perform the tests and feed the weights correctly. Also, the weights must be trained first in some other system, e.g. in a pc using Python or Matlab.

IO

#InputOutputBidirectional
0data_in[0]data_out[0]selector[0]
1data_in[1]data_out[1]selector[1]
2data_in[2]data_out[2]selector_out[0]
3data_in[3]data_out[3]selector_out[1]
4data_in[4]data_out[4]
5data_in[5]data_out[5]
6data_in[6]data_out[6]
7data_in[7]data_out[7]

Chip location

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(RF_peripheral_circuits) tt_um_jleightcap (fractran-tt) tt_um_wokwi_399518371950068737 (Full-adder out of a kmap) tt_um_davidparent_hdl (PRBS Generator) tt_um_adia_psu_seq_test (Adiabatic PSU sequencer test) tt_um_spacecat_chan_john_pong_the_second (John Pong The Second) tt_um_rajum_iterativeMAC (Iterative MAC) tt_um_asinghani_tinywspr (TinyWSPR) tt_um_thatoddmailbox (DuckCPU) tt_um_rejunity_vga (VGA Checkers) tt_um_8bitadder (Ripple Carry Adder 8 bit) tt_um_vzayakov_top (Pong-VGA) tt_um_pa1mantri_cdc_fifo (Clock Domain Crossing FIFO) Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available 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