My School and Instructor: Wright State University EE-4550/6550 IC Hardware Security and Trust by Dr. Saiyu Ren
My employer: Two Six Technologies
My teammates: Celeste Irwin and Nicholas Nissen
This pseudorandom number generator (PRNG) is compromised of scan flip-flops (SFF) and XOR gates. There are two PRNGs in this design, a PRNG with and without a hardware trojans
Test by giving design a clock signal, and then set the PRNG by setting the scanin pins, and then toggle the scan enable pin. To reset turn off all the scanin pins and then leave the scan enable pin on for a few seconds.
Pattern generator and logic analyzer recommended.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Scan Enable | PRNG 1 output Trojan Free | Input, ScanIn 8 |
| 1 | ScanIn 1 | PRNG 2 output trojan inserted | Input, ScanIn 9 |
| 2 | ScanIn 2 | Input, ScanIn 10 | |
| 3 | ScanIn 3 | Input, External Trojan Trigger | |
| 4 | ScanIn 4 | Output, single inverter test | |
| 5 | ScanIn 5 | Input, single inverter test | |
| 6 | ScanIn 6 | Input, 8 inverters test | |
| 7 | ScanIn 7 | Output, 8 inverters test |