102 SRLD

102 : SRLD

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  • Author: Chris Burton
  • Description: 8-bit Shift Register with latch and hex decode to display alternating nibbles
  • GitHub repository
  • Clock: 16 Hz

How it works

Data is inputted to an 8-bit shift register, the data can then be (optionally) latched, data can be switched around if needed based on shifted data being LSB/MSB first, cylcles between decoding high/low nibble to show on the 7-segment display.

How to test

Use shiftIn and shiftClk to clock in 8-bits of data. Toggle latch to move data from shift register to the latch. 7-seg display will show alternating high/low nibbles. If useLatch is high data comes from the latch otherwise it will be shown 'live' as it's shifted in. If cycle_display is low the display will cycle between high/low nibble otherwise it will show the nibble selected by lowHighNibble. mslLsb will switch between showing the shifted data as MSB or LSB first.

External hardware

Switches and 7-segment display

IO

#InputOutput
0displayClocksegment a
1shiftInsegment b
2shiftClksegment c
3latchsegment d
4cycle_displaysegment e
5lowHighNibblesegment f
6useLatchsegment g
7mslLsbHigh/low nibble indicator